Read e-book online Architecture of High Performance Computers: Volume I PDF

By R. N. Ibbett, N. P. Topham (auth.)

ISBN-10: 1489967125

ISBN-13: 9781489967121

ISBN-10: 1489967141

ISBN-13: 9781489967145

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Read Online or Download Architecture of High Performance Computers: Volume I Uniprocessors and vector processors PDF

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Extra resources for Architecture of High Performance Computers: Volume I Uniprocessors and vector processors

Example text

This situation only arises during block copy operations between the Small Core Memory (SCM) and Large Core Memory (LCM) in the 7600 and between Central Storage and the Extended Core Storage in the 6600. In random addressing of the 7600 SCM for instructions, program data and input-output channel data, an average of four SCM banks in operation at one time is more normal. This means that there is a high probability that any single request will be to a free storage bank, and will be serviced immediately, and so much of the benefit of this storage arrangement comes not so much from interleaving per se, but from the fact that the store is made up of a large number of relatively small independent modules.

2) + (n- 1) andin the limit, as the number of data items tends to infinity . T1 k 11m-= T1c n-+oo This defines the asymptotic maximum speedup, in terms of throughput, and this is equal to the number of pipeline stages. In general, of course, the ßow of data items in any real pipeline is subject to disruptions of one kind or another, and maximum throughput cannot be maintained continuously. For a pipeline which processes a finite stream of data items between disruptions we can define two further parameters which characterise its performance: efficiency and net throughput.

12 13 3 9 2 6 5 41 .. 1·:1 ·I where ** indicates an empty core block. If the program called for a virtual address in page 7, for example, the hardware would have been required to translate this into a request to a real address in block 2 of the core store. 2 31 Page address registers In developing the hardware to implement the translation between virtual and real addresses, the designers of Atlas made the following observations 1. Every virtual address generated within the processor has to be translated into a real address by a table look-up, and this involves an extra contribution to the store access time.

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Architecture of High Performance Computers: Volume I Uniprocessors and vector processors by R. N. Ibbett, N. P. Topham (auth.)


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